<?xml version="1.0" encoding="UTF-8"?>
<BuildStatus>
    <Strategy name="my">
        <Milestone name="Export" build_result="0" build_time="0">
            <Task name="IBIS" build_result="0" update_result="3" update_time="0"/>
            <Task name="TimingSimFileVlg" build_result="0" update_result="3" update_time="0"/>
            <Task name="TimingSimFileVHD" build_result="0" update_result="3" update_time="0"/>
            <Task name="Bitgen" build_result="2" update_result="0" update_time="1760683674"/>
            <Task name="Promgen" build_result="0" update_result="3" update_time="0"/>
        </Milestone>
        <Milestone name="Map" build_result="2" build_time="1760655577">
            <Task name="Map" build_result="2" update_result="0" update_time="1760655577"/>
            <Task name="MapTrace" build_result="0" update_result="3" update_time="0"/>
            <Task name="MapVerilogSimFile" build_result="0" update_result="3" update_time="0"/>
            <Task name="MapVHDLSimFile" build_result="0" update_result="3" update_time="0"/>
        </Milestone>
        <Milestone name="PAR" build_result="2" build_time="1760683617">
            <Task name="PAR" build_result="2" update_result="0" update_time="1760683617"/>
            <Task name="PARTrace" build_result="2" update_result="0" update_time="1760683627"/>
            <Task name="IOTiming" build_result="2" update_result="0" update_time="1760683659"/>
        </Milestone>
        <Milestone name="Synthesis" build_result="2" build_time="1760655469">
            <Task name="Lattice_Synthesis" build_result="2" update_result="0" update_time="1760655469"/>
            <Task name="LSE_Compile" build_result="2" update_result="0" update_time="1760683674"/>
        </Milestone>
        <Milestone name="TOOL_Report" build_result="0" build_time="0">
            <Task name="HDLE" build_result="0" update_result="3" update_time="0"/>
            <Task name="BKM" build_result="0" update_result="3" update_time="0"/>
            <Task name="SSO" build_result="0" update_result="3" update_time="0"/>
            <Task name="PIODRC" build_result="0" update_result="3" update_time="0"/>
            <Task name="DEC" build_result="0" update_result="3" update_time="0"/>
        </Milestone>
        <Report name=".vdbs/dsp_fpga_project_impl1_map.vdb" last_build_time="1760655577" last_build_size="8053299"/>
        <Report name="dsp_fpga_project_impl1.bgn" last_build_time="1760683674" last_build_size="4592"/>
        <Report name="dsp_fpga_project_impl1.bit" last_build_time="1760683674" last_build_size="582682"/>
        <Report name="dsp_fpga_project_impl1.ior" last_build_time="1760683659" last_build_size="12450"/>
        <Report name="dsp_fpga_project_impl1.lsedata" last_build_time="1760655397" last_build_size="41657841"/>
        <Report name="dsp_fpga_project_impl1.mcs" last_build_time="1757972749" last_build_size="1602519"/>
        <Report name="dsp_fpga_project_impl1.ncd" last_build_time="1760683617" last_build_size="24820106"/>
        <Report name="dsp_fpga_project_impl1.ngd" last_build_time="1760655469" last_build_size="18879281"/>
        <Report name="dsp_fpga_project_impl1.tw1" last_build_time="1760284129" last_build_size="17553"/>
        <Report name="dsp_fpga_project_impl1.twr" last_build_time="1760683627" last_build_size="138635"/>
        <Report name="dsp_fpga_project_impl1_map.ncd" last_build_time="1760655574" last_build_size="16417325"/>
    </Strategy>
</BuildStatus>
      